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TC55W800XB7,8
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION
The TC55W800XB is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.3 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 0.5 A standby current (at VDD = 3 V, Ta = 25C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of -40 to 85C, the TC55W800XB can be used in environments exhibiting extreme temperature conditions. The TC55W800XB is available in a plastic 48-ball BGA.
FEATURES
* * * * * * * Low-power dissipation Operating: 9.9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.3 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.3 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum):
3.3 V 3.0 V 10 A 5 A
*
Access Times (maximum at VDD = 2.7 to 3.3 V):
TC55W800XB 7 Access Time
CE1 Access Time
8 85 ns 85 ns 85 ns 45 ns
70 ns 70 ns 70 ns 35 ns
CE2 Access Time
OE Access Time
*
Package: P-TFBGA48-0811-0.75AZ (Weight: 0.21 g typ)
PIN ASSIGNMENT (TOP VIEW)
48 PIN BGA
1 A B LB I/O9 2
OE UB
PIN NAMES
3 A0 A3 A5 A17 NC A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2
CE1
6 CE2 I/O1 I/O3 VDD VSS I/O7 I/O8 NC
A0~A18
CE1 , CE2
Address Inputs Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Power Ground No Connection
R/W
OE
C I/O10 I/O11 D E VSS VDD I/O12 I/O13
I/O2 I/O4 I/O5 I/O6 R/W A11
LB , UB I/O1~I/O16 VDD GND NC
F I/O15 I/O14 G I/O16 H A18 NC A8
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BLOCK DIAGRAM
CE A3 A6 A8 A9 A10 A11 A12 A13 A14 A15 A17 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 VDD GND MEMORY CELL ARRAY 2,048 x 256 x 16 (8,388,608)
ROW ADDRESS BUFFER
ROW ADDRESS REGISTER
ROW ADDRESS DECODER
SENSE AMP DATA OUTPUT BUFFER CE A0 A1 A2 A4 A5 A7 A16 A18 I/O9~I/O16 Output Output High-Z Input Input High-Z High-Z High-Z High-Z High-Z DATA INPUT BUFFER
COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER
CLOCK GENERATOR
CE1 CE2
LB
UB
CE
R/W
OE
OPERATING MODE
MODE
CE1
CE2 H H H H H H H * L *
OE
R/W H H H L L L H * * *
LB L H L L H L * * * H
UB
I/O1~I/O8 Output High-Z Output Input High-Z Input High-Z High-Z High-Z High-Z
DATA OUTPUT BUFFER
DATA INPUT BUFFER
POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDS IDDS
L Read L L L Write Output Deselect Standby * = don't care H = logic high L = logic low L L L H * *
L L L * * * H * * *
L L H L L H * * * H
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MAXIMUM RATINGS
SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~4.2 -0.3*~4.2 -0.5~VDD + 0.5 0.6 260 -55~125 -40~85 UNIT V V V W C C C
*: -2.0 V when measured at a pulse width of 25ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C)
SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage VDD = 2.3 V~3.3 V VDD = 2.7 V~3.3 V MIN 2.3 2.0 2.2 -0.3* 1.5 VDD x 0.22 3.3 V V TYP MAX 3.3 VDD + 0.3 UNIT V V
*: -2.0 V when measured at a pulse width of 25ns
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DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 2.3 to 3.3 V)
SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = VDD - 0.5 V VOL = 0.4 V
CE1 = VIH or CE2 = VIL or LB and UB = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE1 = VIL and CE2 = VIH and LB and UB = VIL and R/W = VIH and IOUT = 0 mA and Other Input = VIH/VIL
TEST CONDITION
MIN -0.5 2.1 min tcycle 1 s min tcycle 1 s
TYP 0.05
MAX 1.0 1.0 50
UNIT A mA mA A
lDDO1 Operating Current lDDO2
mA 10 45 mA 5 2 1 10 0.5 1 5 A mA
CE1 = 0.2 V and CE2 = VDD - 0.2 V and LB and UB = 0.2 V, R/W = VDD - 0.2 V and IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V
IDDS1
CE1 = VIH or CE2 = VIL or LB and UB = VIH CE1 = VDD - 0.2 V or CE2 = 0.2 V or LB and UB = VDD - 0.2 V, VDD = 1.5 V~3.3 V
VDD = 3.0 V 10% VDD = 3.0 V
Ta = 25C Ta = -40~85C Ta = 25C Ta = -40~40C Ta = -40~85C
IDDS2 (Note)
Standby Current
Note
In standby mode with CE1 VDD - 0.2 V, these limits are assured for the condition CE2 VDD - 0.2 V or CE2 0.2 V. In standby mode with LB and UB VDD - 0.2 V, these limits are assured for the condition CE1 VDD - 0.2 V or CE1 0.2 V and CE2 VDD - 0.2 V or CE2 0.2 V.
CAPACITANCE (Ta = 25C, f = 1 MHz)
SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF
This parameter is periodically sampled and is not 100% tested.
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(Ta = -40 to 85C, VDD = 2.7 to 3.3 V) READ CYCLE
TC55W800XB SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time 70 5 0 0 10 7 MAX 70 70 70 35 70 30 30 30 MIN 85 5 0 0 10 8 MAX 85 85 85 45 85 35 35 35 ns UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
TC55W800XB SYMBOL PARAMETER MIN tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 70 50 60 60 0 0 0 30 0 7 MAX 30 MIN 85 55 70 70 0 0 0 35 0 8 MAX 35 ns UNIT
AC TEST CONDITIONS
PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 30 pF + 1 TTL Gate 0.4 V, 2.4 V VDD x 0.5 VDD x 0.5 5 ns
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(Ta = -40 to 85C, VDD = 2.3 to 3.3 V) READ CYCLE
TC55W800XB SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time 85 5 0 0 10 7 MAX 85 85 85 45 85 35 35 35 MIN 100 5 0 0 10 8 MAX 100 100 100 50 100 40 40 40 ns UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
TC55W800XB SYMBOL PARAMETER MIN tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 85 55 70 70 0 0 0 35 0 7 MAX 35 MIN 100 60 80 80 0 0 0 40 0 8 MAX 40 ns UNIT
AC TEST CONDITIONS
PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDD x 0.5 5 ns
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TIMING DIAGRAMS
READ CYCLE
(See Note 1)
tRC Address A0~A18 tACC tCO1
CE1
tOH
tCO2 CE2 tOE
OE
tOD
tBA
UB , LB
tODO
DOUT I/O1~16
tBE tOEE Hi-Z tCOE INDETERMINATE
tBD VALID DATA OUT Hi-Z
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
tWC Address A0~A18 tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tODW DOUT I/O1~16 (See Note 2) Hi-Z tDS DIN I/O1~16 (See Note 5)
tOEW (See Note 3) tDH (See Note 5)
VALID DATA IN
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WRITE CYCLE 2 ( CE1 CONTROLLED)
(See Note 4)
tWC Address A0~A18 tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tBE DOUT I/O1~16 Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN I/O1~16
(See Note 5)
VALID DATA IN
WRITE CYCLE 3 (CE2 CONTROLLED)
(See Note 4)
tWC Address A0~A18 tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tBE DOUT I/O1~16 Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN I/O1~16
(See Note 5)
VALID DATA IN
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WRITE CYCLE 4 ( UB, LB CONTROLLED)
(See Note 4)
tWC Address A0~A18 tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tBE DOUT I/O1~16 Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN I/O1~16
(See Note 5)
VALID DATA IN
Note: (1) (2) (3) (4) (5)
R/W remains HIGH for the read cycle. If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
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DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C)
SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.3 V Ta = -40~85C IDDS2 Standby Current VDH = 3.0 V Ta = -40~40C Ta = -40~85C MIN 1.5 0 tRC
(See Note)
TYP
MAX 3.3 10 1 5
UNIT V
A
tCDR tR Note:
Chip Deselect to Data Retention Mode Time Recovery Time Read cycle time
ns ns
CE1 CONTROLLED DATA RETENTION MODE
VDD
(See Note 1)
VDD 2.3 V
DATA RETENTION MODE
(See Note 2) VIH
CE1
(See Note 2) VDD - 0.2 V tR
tCDR
GND
CE2 CONTROLLED DATA RETENTION MODE
VDD
(See Note 3)
VDD 2.3 V CE2 VIH VIL GND
DATA RETENTION MODE
tCDR 0.2 V
tR
Note: (1) (2) (3)
In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 0.2 V or CE2 VDD - 0.2 V. When CE1 is operating at the VIH level, the operating current is given by IDDS1 during the transition of VDD from 2.3 to 2.2V. In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 0.2 V.
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TC55W800XB7,8
PACKAGE DIMENSIONS
P-TFBAG48-0811-0.75AZ
Unit: mm
0.20 S B
11.0 10.9 0.05
7.9 0.05
4-C0.5 4 0.16 0.1 S S
0.25 0.05
0.1 S B
ABCDEFGH
2.125
1
0.75
1.2max
8.0
A
0.4 0.05
3 4 5 6
S AB
0.08
0.75 2.875
0.375 (5.25)
Weight: 0.21 g (typ)
0.375
(3.75)
2
0.20 S A
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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